SYNTHESIZER DESIGN Building a Microwave Frequency Synthesizer — Part 4 : Improving Performance

T his series of articles continues with an analysis of PLL synthesizer design trade-offs. The simple single-loop PLL synthesizer approach exhibits various limitations and trade-offs. Thus, achieving a good performance combination (e.g., small step size and low phase noise) usually requires more sophisticated solutions. The common design trade-offs as well as various methods to improve synthesizer characteristics are discussed. The main PLL synthesizer parameters, such as output frequency range, step size, switching speed, spurious, and phase noise heavily depend on each other. First of all, the synthesizer switching speed is a function of its loop bandwidth, which is, in turn, defined by the phase detector comparison frequency or the step size. Thus, the smaller the step size, the slower the switching speed. Trying to increase the loop bandwidth may lead to higher reference spurs due to insufficient loop filter rejection. Clearly, increasing the phase detector comparison frequency will benefit the switching speed and spurious performance. On the other hand, for a simple single-loop PLL the phase detector frequency equals to the frequency step size and, therefore, can not be arbitrarily increased. A simple solution to overcome this problem is presented in Figure 37. The idea is to increase both phase detector input and VCO output frequencies by K times, and then bring the synthesizer output frequency and step size down to desired numbers with an additional divider. This scheme allows higher phase detector comparison frequencies that lead to improved performance, e.g., faster tuning speed or better spur rejection. Besides, it can potentially provide better phase noise characteristics too. Although the phase detector noise normally exhibits 10logK degradation with the phase detector comparison frequency increase, this degradation will be offset by a factor of 20logK by the output frequency divider. Assuming that the phase detector noise dominates (in certain cases) and the loop division coefficient N remains unchanged, the scheme will demonstrate 10logK overall noise improvement. Let's step back to the general single-loop PLL case (Fig. 15). The main impact on the synthesizer performance is posted by large division ratios required to provide a high-frequency output with a fine resolution. For example, in order to get 10 GHz output with 1 MHz step size, the feedback divider ratio has to be 10000 that corresponds to 80 dB phase noise degradation. Moreover, programmable dividers are usually not available at high frequencies , thus an additional fixed divider (prescaler) is required. In this …